The present invention relates generally to the field of semiconductor wafer manufacture processes, and more particularly to predicting process fail limits for multiple semiconductor manufacturing processes.
The fabrication of integrated circuits on a semiconductor wafer includes numerous process steps such as photolithography steps (in future references, “photolithography” is referred to as “lithography”). Lithography systems for lithography processing generally involve tools and processes to expose a desired pattern onto a resist layer on a semiconductor wafer, develop the resist layer, and remove the portions of the resist exposed (or, not exposed depending on the resist type). Then, following the lithography processes, further processing of the semiconductor wafer occurs, for example, by etching the underlying layer, implanting elements or depositing additional material using the developed resist layer. The processes to expose a pattern on a resist layer are commonly performed using a step and scan exposure tool such as a lithography stepper. A lithography stepper generally exposes a lithography mask or reticle by scanning a slit of fixed width from one end of the lithography mask to the other or, in some cases, by keeping the slit fixed and moving the wafer. Many multiple exposures of a mask commonly occur on a single semiconductor wafer. Lithography imaging is highly dependent on wafer surface uniformity and circuit design elements to be processed, such as component or wafer patterns such as line width, line spacing, circuit elements (e.g., microprocessors, cache, or deep trench capacitors), and the adjacent wafer features.
As integrated circuits increase in density, each successive generation of integrated circuits reduce the size of device circuit elements or device features such as lines and spaces on a semiconductor wafer. When a lithography system attempts to print circuit elements or wafer features having sizes near the wavelength of the exposing radiation, the resulting shapes of the printed circuit elements become significantly different from the corresponding pattern on the mask. For example, line width of circuit elements may vary depending on the proximity of adjacent lines causing inconsistent or different operation speeds for lines designed with the same width in a semiconductor device. For another example, line ends tend to shorten or “pullback”. As the lines become smaller, this pullback becomes more significant, in some cases, causing open connections or weaker connections that are more failure prone.
Optical proximity correction (OPC) was developed to apply systematic changes to the mask to compensate for non-linear distortions caused by optical diffraction and resist process effects. OPC works by making changes to the as-designed integrated circuit layout that anticipate and correct for the distortions. Determining optimal feature types and sizes by OPC is extremely complex depending on neighboring geometries and process parameters and requires a sophisticated, complex computer program. Model-based verification or optical rules checking (ORC) is an approach in which shape checking is implemented on simulated wafer images. Although simulated wafer images of OPC enhanced layout shapes provide qualitative insight into the patterning of many layout shapes, it is extremely difficult to guarantee that all of the millions of shapes on a mask yield functional circuitry.